Access latency after a miss in the 元 cache is 30 - 32ns, nicely in between an 元 and main memory access.
Intel isn’t providing much detail on the connection to Crystalwell other than to say that it’s a narrow, double-pumped serial interface capable of delivering 50GB/s bi-directional bandwidth (100GB/s aggregate). That’s right, Haswell CPUs equipped with Crystalwell effectively have a 128MB L4 cache. discrete GPU installed), Crystalwell will still work on caching CPU requests. The cache can dynamically allocate its partitioning between CPU and GPU use. It acts as a victim buffer to the 元 cache, meaning anything evicted from 元 cache immediately goes into the L4 cache. Unlike previous eDRAM implementations in game consoles, Crystalwell is true 4th level cache in the memory hierarchy. If Crystalwell demand is lower than expected, Intel still has a lot of quad-core GT3 Haswell die that it can sell and vice versa. By making Crystalwell (the codename for the eDRAM silicon) a discrete die, it’s easier to respond to changes in demand. Intel needed a set of low leakage 22nm transistors rather than the ability to drive very high frequencies which is why it’s using the mobile SoC 22nm process variant here.ĭespite its name, the eDRAM silicon is actually separate from the main microprocessor die - it’s simply housed on the same package. The eDRAM itself is a custom design by Intel and it’s built on a variant of Intel’s P1271 22nm SoC process (not P1270, the CPU process). As a owner of several bleeding edge foundries, would you expect anything less?Īs we’ve been talking about for a while now, the highest end Haswell graphics configuration includes 128MB of eDRAM on-package. Intel’s solution to the problem, like most of Intel’s solutions, involves custom silicon. As Haswell is predominantly a mobile focused architecture, designed to span the gamut from 10W to 84W TDPs, relying on a power-hungry high-speed external memory interface wasn’t going to cut it. Integrated graphics solutions always bumped into a glass ceiling because they lacked the high-speed memory interfaces of their discrete counterparts.